The present invention relates to a semiconductor memory device and a semiconductor integrated circuit including the semiconductor memory device. In particular, the present invention relates to a technology of effectively reducing leakage current of transistors in the case of using high-integration, high-density devices of a design rule in the generation of 0.13 xcexcm gate length or later and operating at a power supply voltage as low as 1.2 V or less.
In general, to operate a semiconductor memory device at high speed even under low voltage, technologies using transistors having a low threshold voltage as its constituent transistors are adopted.
Use of a transistor having a low threshold voltage causes a problem that a large amount of OFF leakage current flows between the source and the drain of the transistor even during OFF periods. To solve this problem, conventionally, a negative voltage is set for word lines, and the source potential is shifted toward a positive potential, for example, to thereby effectively apply a negative bias to the transistor and thus limit the OFF leakage current to a small value.
Applying a large negative voltage to word lines and shifting the source voltage toward a positive potential are effective technologies producing no side effect when the device is sufficiently resistant to voltages. However, as the gate oxide film is thinned to below 2 nanometers with implementation of finer devices, a problem of gate leakage caused by a tunnel current arises. The conventionally proposed technology of driving word lines with a negative voltage and technology of offsetting source lines mentioned above increase the gate-source potential difference. Therefore, while succeeding in minimizing the OFF leakage current, these technologies disadvantageously cause a problem of increasing the gate leakage current.
With implementation of finer devices, the electric field between the gate and the drain of a transistor increases. This gives rise to a problem of gate-induced drain leakage (GIDL) current generated when a large potential difference is applied between the gate and the drain. The conventional technologies such as driving word lines with a negative voltage further induce this GIDL current, and thus have another problem of failing to minimize this new leakage current.
Leakage current from bit lines especially causes a problem. During data read operation, whether or not the potential of a precharged bit line has been drawn by a cell current is determined. Therefore, if there exists an amount of leakage current too large to be negligible with respect to the cell current, it is difficult to distinguish the cell current from the leakage current. As a result, it may take a long time before data read or erroneous data read may occur.
An object of the present invention is providing a semiconductor memory device capable of limiting gate leakage current and GIDL current to a small value while effectively limiting OFF leakage current.
To attain the object described above, in a semiconductor memory device of the present invention, the negative potential of non-selected word lines and the precharge potential of non-selected bit lines are appropriately set considering three types of leakage current, that is, OFF leakage current, gate leakage current and GIDL current. In addition, the potential of source lines of memory cells are appropriately set.
The semiconductor memory device of the present invention includes: a plurality of memory cells each drawing cell current according to data stored therein when selected; a plurality of word lines and a plurality of bit lines selected for accessing data in a specific memory cell among the plurality of memory cells; a power supply for providing a voltage corresponding to a high-level side potential of data in the plurality of memory cells; a word line potential supply source for supplying a potential to the plurality of word lines; and a precharge potential supply source for supplying a precharge potential to the plurality of bit lines, wherein a precharge potential supplied to non-selected bit lines among the plurality of bit lines by the precharge potential supply source is set at a value lower than the voltage of the power supply, a potential supplied to non-selected word lines among the plurality of word lines by the word line potential supply source is set at a predetermined negative value, and a total of the absolute value of the precharge potential of the non-selected bit lines supplied by the precharge potential supply source and the absolute value of the potential of the non-selected word lines supplied by the word line potential supply source is a value less than the voltage of the power supply.
In the semiconductor memory device described above, the precharge potential of the non-selected bit lines supplied by the precharge potential supply source may be set at a value less than half of the voltage of the power supply.
In the semiconductor memory device described above, a precharge potential supplied to a selected bit line among the plurality of bit lines by the precharge potential supply source may be set at a value higher than the precharge potential supplied to the non-selected bit lines by the precharge potential supply source and equal to or more than the half of the voltage of the power supply.
In the semiconductor memory device described, each of transistors constituting the plurality of memory cells may be constructed of a transistor in which the difference in current amount per unit gate width between OFF leakage current and gate leakage current is within two orders of magnitude.
In the semiconductor memory device described above, the voltage of the power supply may be 0.5 V to 1.2 V.
In the semiconductor memory device described above, the negative potential supplied to the non-selected word lines by the word line potential supply source may be changed depending on ambient temperature.
In the semiconductor memory device described above, the absolute value of the negative potential supplied to the non-selected word lines by the word line potential supply source may be larger when the ambient temperature is high than when it is normal.
Alternatively, the semiconductor memory device of the present invention includes: a plurality of memory cells each drawing cell current according to data stored therein when selected; a plurality of word lines and a plurality of bit lines selected for accessing data in a specific memory cell among the plurality of memory cells; a power supply for providing a voltage corresponding to a high-level side potential of data in the plurality of memory cells; a plurality of source lines for providing a low-level side potential of data in the plurality of memory cells; a word line potential supply source for supplying a potential to the plurality of word lines; a precharge potential supply source for supplying a precharge potential to the plurality of bit lines; and a source potential supply source for supplying a potential to the plurality of source lines, wherein a precharge potential supplied to non-selected bit lines among the plurality of bit lines by the precharge potential supply source is set at a value lower than the voltage of the power supply, a potential supplied to non-selected word lines among the plurality of word lines by the word line potential supply source is set at a predetermined negative value, a potential supplied to non-selected source lines among the plurality of source lines by the source potential supply source is set at a predetermined positive value, a total of the absolute value of the precharge potential of the non-selected bit lines supplied by the precharge potential supply source and the absolute value of the potential of the non-selected word lines supplied by the word line potential supply source is set at a value less than the voltage of the power supply, and the absolute value of the potential of the non-selected word lines supplied by the word line potential supply source and the absolute value of the potential of the non-selected source lines supplied by the source potential supply source are roughly equal to each other.
The semiconductor memory device described above may further include a row decode circuit for selecting a word line from the plurality of word lines according to a row address received, wherein selection and non-selection of the plurality of source lines is performed based on the row address.
The semiconductor memory device described above may further include a column decoder for selecting a bit line pair from the plurality of bit lines according to a column address received, wherein selection and non-selection of the plurality of source lines is performed based on the column address.
In the semiconductor memory device described above, the positive potential supplied to the non-selected source lines by the source line potential supply source may be changed depending on ambient temperature.
In the semiconductor memory device described above, the positive potential supplied to the non-selected source lines by the source line potential supply source may be larger when the ambient temperature is high than when it is normal.
In the semiconductor memory device described above, the semiconductor memory device may be used for portable equipment having a normal operation mode and a standby mode, and the potential may be changed depending on the ambient temperature for the normal operation mode and the standby mode separately.
The semiconductor integrated circuit of the present invention includes: a semiconductor memory including a plurality of memory cells, a plurality of word lines and a plurality of bit lines selected for accessing data in a specific memory cell among the plurality of memory cells, a decode circuit for selecting any word line from the plurality of word lines, and a word line drive circuit for driving the selected word line in response to an output of the decode circuit received; and a semiconductor circuit including a transistor having a low threshold voltage and a transistor having a high threshold voltage, wherein the decode circuit of the semiconductor memory has a transistor of which a source line is connected to the ground potential, the transistor being constructed of a transistor having a low threshold voltage of the same type as the transistor having a low threshold voltage included in the semiconductor circuit, and the word line drive circuit of the semiconductor memory has a pull-down transistor of which a source line for pulling down the potential of the word line is connected to a negative potential supply line, the pull-down transistor being constructed of a transistor having a high threshold voltage of the same type as the transistor having a high threshold voltage included in the semiconductor circuit.
In the semiconductor integrated circuit described above, the absolute value of the high threshold voltage of the pull-down transistor of the word line drive circuit may be equal to or larger than the absolute value of the potential of the negative potential supply line.
In the semiconductor integrated circuit described above, the pull-down transistor of the word line drive circuit may include a parallel circuit having: a transistor having a low threshold voltage of which a source line is connected to the ground line; and a transistor having a high threshold voltage of which a source line is connected to the negative potential supply line.
In the semiconductor integrated circuit described above, in the semiconductor circuit, the transistor having a low threshold voltage may be a transistor including a gate oxide film or threshold adjusting impurity formed for a transistor constituting a logic circuit that is high in leakage current but operates at high speed, and the transistor having a high threshold voltage may be a transistor including a gate oxide film or threshold adjusting impurity formed for a transistor constituting a logic circuit that operates at low speed but is low in leakage current.
In the semiconductor integrated circuit described above, in the semiconductor circuit, the transistor having a low threshold voltage may be a transistor including a gate oxide film or threshold adjusting impurity formed for a transistor constituting a logic circuit, and the transistor having a high threshold voltage may be a transistor including a gate oxide film or threshold adjusting impurity formed for a transistor constituting an analog circuit and/or an I/O circuit.
In the semiconductor integrated circuit described above, the power supply voltage supplied to the semiconductor memory and the semiconductor circuit may be 0.5 V to 1.2 V.
In the semiconductor integrated circuit described above, the semiconductor memory device may be an SRAM.
In the semiconductor integrated circuit described above, the semiconductor memory device may be a ROM.
Alternatively, the semiconductor integrated circuit of the present invention includes the semiconductor memory device described above and a semiconductor circuit including a transistor having a low threshold voltage and a transistor having a high threshold voltage, wherein the absolute value of the negative potential supplied to the non-selected word lines by the word line potential supply source of the semiconductor memory device is equal to or smaller than the absolute value of the high threshold voltage of the transistor of the semiconductor circuit.
According to the present invention, the precharge potential of the non-selected bit lines is set at a low value below the power supply voltage, and the pull-down potential of the non-selected word lines is set at a negative value. In addition, the total of the precharge potential of the non-selected bit lines and the absolute value of the negative potential of the non-selected word lines is set at a value less than the power supply voltage. By these settings, gate leakage current and GIDL current can be effectively limited to a small value while realizing effective limitation of OFF leakage current. Therefore, even when charge on the precharged bit lines is discharged by some amount by gate leakage current, the gate leakage current will be clearly distinguished from a cell current that has a meaning as data, and thus data read can be executed as originally intended swiftly and correctly. Moreover, even when GIDL current is generated to some extent from a storage node retaining xe2x80x9cHxe2x80x9d data in the SRAM to the substrate, a cell current will not be reduced so much, and thus data read can be executed as originally intended.
In particular, according to the present invention, the potential of the non-selected source lines is set at a positive value roughly equal to the absolute value of the potential of the non-selected word lines. This effectively limits OFF leakage current to a small value compared with the case of setting the potential of the non-selected source lines at the ground potential.
Moreover, according to the present invention, the negative potential supplied to the non-selected word lines and the positive potential supplied to the non-selected source lines are changed depending on the ambient temperature of the semiconductor memory device. This enables effective limitation of OFF leakage current, gate leakage current and GIDL current to a small value irrespective of change of the ambient temperature.
In addition, according to the present invention, when a negative potential is set for the non-selected word lines, the absolute value of the negative potential is made small as described above compared with the conventional case. Therefore, the transistor constituting the decode circuit of the semiconductor memory can be constructed of a transistor having a low threshold voltage of the same type as the transistor having a low threshold voltage originally included in the semiconductor circuit, and the pull-down transistor of the word line drive circuit of the semiconductor memory can be constructed of a transistor having a high threshold voltage of the same type as the transistor having a high threshold voltage included in the semiconductor circuit. Accordingly, the number of transistors used to constitute the word line drive circuit can be small and thus the layout area can be reduced, compared with the conventional word line drive circuit.